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MDB1900Z Zero Delay Buffer for PCIe Gen1/2/3 and Intel QPI Applications

General Description:
The MDB1900Z is a true zero delay buffer with fully integrated high performance, low power and low phase noise programmable PLL.
The device is capable of distributing the reference clocks for PCIe (Gen1/Gen2/Gen3), SATA, ESI, SAS, SMI and Intel Quick Path Interconnect (QPI). The MDB1900Z works in conjunction with CK410B+, CK509B or CK420BQ clock Synthesizer to provide reference clocks to multiple agents.

  • 100 MHz or 133.33 MHz (0.7 V) differential input reference
  • Nineteen differential clock output pairs @ 0.7 V (HCSL compatible)
  • Output frequencies: 100 MHz or 133.33 MHz
  • Supports zero delay buffer (PLL) mode and fan-out buffer (bypass) mode
  • Dedicated feedback output and input pins for ZDB in PLL mode
  • Spread spectrum modulation tolerant
  • Programmable PLL bandwidth
  • 9 selectable SMBus addresses
  • Power management control
  • Glitch free transition on OE# assertion/de-assertion
  • 3.3 V or 2.5V operation
  • Industrial temperature range (- 40 °C to 85 °C)
  • 72 pin QFN package
  • Green, RoHS compliant and PFOS compliant
  • Output cycle-cycle jitter (PLL mode) 25 ps
  • Output to output skew 18 ps
  • PLL jitter peaking 1dB
  • PCIe Gen2 phase jitter 0.9 ps (Low Frequency Jitter LFJ)
  • PCIe Gen2 phase jitter 1.1 ps (High Frequency Jitter HFJ)
  • PCIe Gen3 phase jitter 0.25 ps
  • QPI accumulated jitter (8.0 Gb/s) 0.9 ps
  • QPI accumulated jitter (9.6 Gb/s) 0.8 ps
  • Input-to-output delay (PLL mode) ± 15 ps
  • Input-to-output delay variation (PLL mode) 13 ps
  • Random differential tracking error < 3.5 ps
  • Differential spread spectrum tracking error < 60 ps