MPS14 Dual-PLL Precision Any Frequency Synthesizer

The MPS14 is a dual-PLL programmable synthesizer intended for jitter attenuation and asynchronous clocking applications in high performance telecommunications, networking, data storage, SERDES and PHY applications. The device incorporates two low jitter PLLs that provide any frequency up to 938MHz with precision better than 0.1ppb. Each PLL integrates a 1:2 fanout buffer with integer dividers and mix-and-match programmable outputs that provide LVPECL/LVDS/HCSL/CMOS output formats, delivering maximum flexibility and jitter performance in a compact 7x7mm 48-pin QFN package.

Each output is independently programmable to provide frequencies up to 938 MHz with 266fs to 450fs  RMS jitter (12KHz to 20MHz) utilizing compact, low cost fundamental mode XTALs that enable a robust supply chain. Using optional integer frequency synthesis, the MPS14 is capable of achieving jitter as low as 225fs.

The MPS14 DigiPull functionality enables numerically controlled frequency pulling applications using the fast SPI bus. FPGAs and other devices can take advantage of this function to implement digital PLLs with configurable loop bandwidths for jitter attenuation applications, precision disciplined clocks that lock to tight stability references or digitally controlled precision timing applications such as network timing, timing over packet and IEEE1588 applications. The SPI bus operates up to 6MHz, enabling fast FPGA loops while multiple devices share the same bus. Multi-rate precision applications such as broadcast video or OTN can also use the MPS14. HDL FPGA code for digital PLL applications available from Multigig.

Dual any frequency precision synthesis

  • 12 MHz to 938 MHz
  • Better than 0.1ppb resolution

Ultra-low RMS jitter (12k to 20 MHz)

  • 225fs using integer synthesis
  • 266fs to 450fs using fracional synthesis

Supports low cost and compact XTALs

  • 22 to 54 MHz fundamental, non-pullable
  • XTAL packages from 2.5x2.0mm

DigiPull numerical frequency control

  • Dynamically pullable output frequency enables FPGA-based PLLs (HDL available)
  • Fast SPI bus (up to 6 MHz)
  • On-the-fly frequency changes

Dual PLL in compact 7x7mm package

  • Replaces multiple large clock ICs, PLLs, fanout buffers, XOs, and VCXOs

Mix-and-match output buffers

  • In-circuit programmable LVPECL/LVDS/HCSL/CMOS
  • Independent buffer VDDO drives multipletechnologies

Enhanced VDD noise rejection

  • FPGA-based jitter attenuators
  • Precision-disciplined clocks
  • Multi-rate asynchronous clock synthesizer
  • Optical: OTN/SDH/SONET
  • Broadcast video: 3G SDI, HD SDI, SDI
  • Networking and storage: Ethernet/SAS/Fiberchannel
  • Wireless infrastructure: OBSAI/CPRI
  • Industrial: IEEE1588
  • Low Jitter Clocks